The present application relates generally to semiconductor devices, and more specifically to semiconductor fin field effect transistors (FinFETs) and their methods of production.
As bulk FinFET technologies scale, fin pitch scaling is an important aspect of both area and performance scaling. However, fin pitch scaling typically results in a significant increase in the intra-fin aspect ratio, which increases the propensity for void formation during material deposition into high aspect ratio features, the retention of residual deposits following material removal from such features, and/or the deformation of free-standing, high aspect ratio fins during rinsing, handling, etc. The formation of voids and the accumulation of unwanted etch residues may adversely affect device performance and reliability.
In view of the foregoing, it would be advantageous to provide a robust and scalable FinFET manufacturing process that minimizes defect formation and the likelihood of fin deformation during fabrication.